1. Field of the Invention
The present invention relates to a gate array system and a layout method thereof and, more particularly, to a gate array system in which functional blocks disposed at specific positions are connected by fixed wiring using a fixed layout pattern prepared in advance and a layout method thereof.
2. Description of the Related Art
A gate array system implemented on a semiconductor chip includes a lattice array of internal cells, an array of input/output circuit cells (hereinafter referred to as I/O cell) disposed surrounding the lattice array of the internal cells for receiving a signal from and transferring a signal to these internal cells, and a bonding pad array disposed on the circumference of the semiconductor chip surrounding the array of the I/O cells for connecting the gate array system and an external circuit. These configurations are made up in advance by the manufacturing processes on a uniform mass-production basis. In addition, for the manufacture of various gate array systems, a plurality of types of semiconductor chips of difference sizes are prepared by the manufacturing processes on a mass-production basis.
FIG. 7 is a partial layout diagram showing an example of structure of the above-described conventional gate array. On the gate array system illustrated in FIG. 7, connecting functional blocks formed on internal cells 702 is possible by mechanical automatic wiring, fixed wiring using a specific layout pattern, or other arbitrary means. However, connection of a functional block formed at a corner of a semiconductor chip 701 or on an I/O cell 703 with a functional block formed on the internal cell 702 in the vicinity of the former functional block by automatic wiring is difficult because of the crowdedness of a wiring area at this region or because of difficulty in satisfying desired electric characteristics. For connecting functional blocks formed at this region, it is a conventional practice to manually modify the connection which is once made by automatic wiring, or conduct manual wiring from the beginning, or conduct fixed wiring using a fixed layout pattern prepared in advance for the wiring of the region in question.
In conducting fixed wiring using a fixed layout pattern, the above-described conventional gate array system implements a desired function without automatic wiring by making a functional block formed at an internal cell region or a functional block formed at an I/O cell region have a layout pattern of fixed wiring for the wire connection and disposing the functional block at an appropriate position. However, because the distance between an internal cell and an I/O cell varies with the size of a semiconductor chip, as will be described later, it is necessary to prepare in advance as many fixed layout patterns of the parts in question that implement the same function as the number of sizes of a semiconductor chip.
Internal cells and I/O cells are optimized according to a manufacturing process and a circuit in which they are used and are designed to be of minimum size for the purpose of increasing the integration density. As a result, a distance between an internal cell and an I/O cell is not always constant on a semiconductor chip of each size, considering the sizes of a semiconductor chip, internal cells and I/O cells. The reasons are as follows.
Assume, for example, that a semiconductor chip of a gate array system with the size of 8.3 mm.times.8.3 mm is A chip and a semiconductor chip with the size of 14.9 mm.times.14.9 mm is B chip. On both of the A and B chips, the size of an internal cell is assumed to be 7.4 .mu.m.times.28.6 .mu.m, the size of an I/O cell to be 100 .mu.m.times.368.7 .mu.m and the distance from the edge of the semiconductor chip to the edge of the I/O cell to be 160 .mu.m. As a result, the internal cells are arranged in a lattice array symmetrically to the center of the semiconductor chip. Here, if the distance in the X direction of the semiconductor chip between the internal cell and the I/O cell is represented as Dx and the distance in the Y direction between the internal cell and the I/O cell as Dy, the A chip will have Dx of 51.5 .mu.m and Dy of 59.1 .mu.m, while the B chip will have Dx of 51.3 .mu.m and Dy of 50.3 .mu.m, which are different from each other.
If a value obtained by subtracting the size of the I/O cell and the distance between the edge of the semiconductor chip and the edge of the I/O cell from the size of the semiconductor chip is represented as K, Dx will have a value obtained by subtracting, from K, a value obtained by multiplying the size in the X direction of the internal cell by the number of lattice arrays in the X direction of the internal cells in question, while Dx will similarly have a value obtained by subtracting, from K, a value obtained by multiplying the size in the Y direction of the internal cells by the number of lattice arrays in the Y direction of the internal cells in question. Concrete calculation of the distance Dx in the X direction between the internal cell and the I/O cell on the A chip results in K=8300/4-368.7-160=1546.8 .mu.m. Assuming the optimum number of arrays in the X direction of the internal cells to be 202, then Dx=K-7.4.times.202=51.5 .mu.m.
General expression of these relationships is given in the X direction of the semiconductor chip. As illustrated in FIG. 7, formed in advance on the semiconductor chip 701 by the manufacturing processes on a mass-production basis are a lattice array of internal cells 702, an array of I/O cells 703 disposed surrounding the lattice array for receiving a signal from and transferring a signal to the internal cells 702, and an array of bonding pads 704 disposed on the circumference of the semiconductor chip surrounding the array of the I/O cells 703 for connecting the circuits formed on the semiconductor chip 701 with an external circuit. If the size of the semiconductor chip 701 in the X direction is represented as X1, the size of the internal cell 702 in the X direction as X2, the number of arrays of internal cells in the X direction as nx and the distance in the X direction from the edge of the semiconductor chip 701 to the edge of the I/O cell 703 as X3, the relationship X1=2.times.Dx+nx.times.X2+2.times.X3 holds. Here, the conditions for maintaining the distance Dx to be constant with the value of X1 largely depend on the size of the internal cell 702. Taking into account of the fact that the size of the internal cell 702 is minimized for the purpose of increasing the integration density, obtaining a constant distance Dx is very difficult. While general description has been made with respect to the X direction in the foregoing, this is also the case with the Y direction.
FIG. 8 is a flow chart showing a layout method for implementing a desired function on a conventional gate array system by wiring a functional block formed at a corner of the semiconductor chip or on an I/O cell and a functional block formed on an internal cell in the vicinity of the former block.
First, select a functional block optimum for implementing a desired function (Step 801). The functional block used in this example is designed to include, in its internal region, a fixed layout pattern for the wire connection. Next, determine automatic locating and wiring information, using wiring information included in the functional block (Step 802). Then, conduct automatic locating and wiring, using the determined automatic locating and wiring information (Step 803).
The above-described conventional gate array system and layout method thereof, however, have the following drawbacks when implementing a desired function by wiring a functional block formed at a corner of a semiconductor chip or on an I/O cell and a functional block formed on an internal cell in the vicinity of the former block.
Firstly, the conventional gate array system requires as many fixed layout patterns of functional blocks in question which implement the same function to be prepared in advance as the number of sizes of a semiconductor chip. The reason is that since a distance in layout between an internal cell and an I/O cell varies with each size of a semiconductor chip, a gate array system should cope with a difference in distance in layout when conducting fixed wiring using a fixed layout pattern included in a functional block. This results in an increase in the number of steps for designing the fixed layout pattern of the functional block, that is, results in a reduction in efficiency. Moreover, there would exist numbers of similar functional blocks that only differ in wiring of a fixed layout pattern, which causes a designing error to be liable to occur.
Secondly, since wires are crowded at a corner of a semiconductor chip or in the vicinity of an I/O cell, there are cases where automatic wiring is impossible and where required electric characteristics are not satisfied. Repetition of re-wiring processing or manual wiring of some part or the whole part is therefore necessary and numerous designing steps and enormous designing time cause a reduction in efficiency.
Thirdly, the layout method of the conventional gate array system employs neither information regarding a positional relationship between an internal cell and an I/O cell nor information regarding a locating position of a functional block at the time of layout. For locating functional blocks at optimum positions, therefore, their locating positions should be designated one by one, which requires a larger number of designing steps and makes a designing error more likely to occur.